In the fabrication of semiconductor devices, numerous conductive device regions and layers are formed in or on a semiconductor substrate. The conductive regions and layers of the device are isolated from one another by insulating layers or dielectric. Examples of dielectrics include silicon dioxide, SiO.sub.2, tetraethyl orthosilicate glass ("TEOS"), silicon nitrides, Si.sub.x N.sub.y, silicon oxynitrides, SiO.sub.x N.sub.y, silicon dioxide/silicon nitride/silicon dioxide ("ONO"), and spin on glass ("SOG"). The dielectrics may be grown, or may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")). Additionally, the dielectrics may be undoped or may be doped, for example with boron, phosphorous, or both, to form, for example, borophosphosilicate glass ("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl orthosilicate glass ("BPTEOS").
At several stages of the fabrication of semiconductor devices, it is necessary to make openings in the dielectric to allow for contact to underlying regions or layers. Generally, an opening through a dielectric exposing a diffusion region or an opening through a dielectric layer between polysilicon and the first metal layer is called a "contact opening", while an opening in other oxide layers such as an opening through an intermetal dielectric layer is referred to as a "via". The opening may expose a device region within the silicon substrate, such as a source or drain, or may expose some other layer or structure, for example, an underlying metallization layer, local interconnect layer, or structure such as a gate. For purposes of the claimed invention, "contact opening" as used herein refers to both contact openings and via. After the contact opening has been formed exposing a portion of the region or layer to be contacted, the opening is generally cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the opening is filled with a conductive material deposited in the opening and in electrical contact with the underlying region or layer.
To form the openings a patterning layer of photoresist is first formed over the dielectric layer having openings corresponding to the regions of the dielectric where the openings are to be formed. In most modern processes a dry etch is then performed wherein the wafer is exposed to a plasma, formed in a flow of one or more gases. Typically, one or more halocarbons and/or one or more other halogenareal compounds are used as the etchant gas. For example, CF.sub.4, CHF.sub.3 (Freon 23), SF.sub.6, NF.sub.3, and other gases may be used as the etchant gas. Additionally, gases such as O.sub.2, Ar, N.sub.2, and others may be added to the gas flow. The particular gas mixture used will depend on, for example, the characteristics of the dielectric being etched, the stage of processing, the etch tool being used, and the desired etch characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
Circuit elements (i.e., transistors, resistors, diodes, capacitors, etc.) are conductively linked through an interconnect or a series of interconnects through the contact openings or via through dielectric layers to an active region of an element, for example a source or drain. A conductive material or plug is deposited in the contact opening so that the conductive material or plug is electrically linked to the circuit element, and extends through the opening or via to the interconnect. The interconnects are metal (usually aluminum or titanium) and are formed by depositing a layer of the metal on the entire top surface portion of a wafer, and etching the metal to form the desired architecture that serves as the conductors between the various elements of each integrated circuit. In multilayer integrated circuits, multilayer interconnects are used to interconnect the various elements. Multilayering the interconnects maximizes the number of interconnects per unit area and reduces die size.
Modern integrated circuit structures strive to minimize the feature size of the structure to increase device processing performance and reduce production costs. The significant reduction in the size of the device features requires that contact holes be positioned close together, be of small diameter, and have steep vertical sidewalls. The size and shape of these contact holes makes it difficult to deposit conventional materials (i.e., aluminum) in the holes such that a uniform contact with the underlying conductive region or layer is established and no breaks occur in the interconnect metallization at the edges of the holes. This is partially overcome in the prior art by filling, for example, the contact holes with a separate plug fill material such as tungsten and then depositing an aluminum metallization over the plug to form an interconnect (see for example U.S. Pat. Nos. 4,822,753 and 4,960,732). A second method includes the deposition of tungsten plug fill material over an underlying conductive film (e.g., titanium, titanium-nitride, titanium-tungsten, etc.) and the deposition of an additional conductive layer (e.g., titanium, titanium-nitride, titanium-tungsten, aluminum, etc.) over the plug and patterned to form an interconnect between via plugs. A third method is the use of tungsten for both the plug fill material and the interconnect wiring layer (see for example U.S. Pat. Nos. 4,940,732 and 5,183,782). A fourth method utilizes an adhesion layer comprising the deposition of titanium within a contact hole, a barrier layer of a refractory metal, deposition and selective etch-back of tungsten, and a subsequent overlying aluminum metallization (see for example U.S. Pat. No. 4,960,732).
A fifth method of making interconnects with increased speed, no interface barriers, and minimal disruption of the planarity of the semiconductor device is a titanium, titanium-tungsten or -nitride, tungsten contact/interconnect described in the patent application of Jonathan Bornstein and Roger Caldwell, titled "A Method for the Formation of Interconnects and Landing Pads Having a Thin, Conductive Film Underlying the Plug of an Associated Contact or Via Hole", and filed Aug. 29, 1994, given Ser. No. 08/297,626, now U.S. Pat. No. 5,514,622, and assigned to Cypress Semiconductor, Inc., incorporated herein by reference. FIG. 1 illustrates the contact and interconnect described in the referenced application. FIG. 1 shows a cross-sectional planar side view of a portion of a silicon substrate having at least one device region 110 formed at the surface of the substrate. A first insulating layer 120 is deposited over the substrate having a contact hole 130 formed through the insulating layer to expose the device region. A first blanket layer of titanium 140 is deposited as a tungsten adhesion layer over the insulating layer and the exposed device region within the contact hole, this adhesion layer 140 being formed to a thickness of approximately 1,400 Angstroms (.ANG.). A second blanket layer 150 of titanium-tungsten or titanium-nitride is then deposited as a tungsten barrier layer over the adhesion layer. This barrier layer 150 preferably comprises a thickness of approximately 800 Subsequently, a blanket contact plug layer 160 comprising tungsten is deposited to a preferred thickness of approximately 8,000 .ANG. over the barrier layer by chemical vapor deposition.
Both the contact plug layer 160 and the barrier layer 150 are then removed from the surface of the adhesion layer everywhere except within the contact hole 130 by a selective etch back process wherein a selectivity between tungsten and titanium of at least 5:1 is achieved. This is accomplished by use of a SF6 gas chemistry and etch parameters comprising a gas flow of 100 to 300 sccm, a chamber pressure of 200 to 400 mTorr, a 13.56 RF power of 350 to 550 Watts and a chamber temperature of 30.degree. to 50.degree. Celsius. Next, the exposed portions of the titanium adhesion layer 140 are patterned with a mask and etched to remove those portions of the adhesion layer 140 not covered by the mask, thus converting the adhesion layer 140 into a thin film interconnect having a thickness of approximately 1,000 Angstroms and underlying the contact plug of the associated contact hole. Although it has been described as an adhesion layer, it should also be noted that titanium provides good electrical contact and acts as an etch stop for the plasma etching of tungsten.
A still further method of making interconnects is by a Damascene process. Briefly, the Damascene process involves creating a trench adjacent to the contact hole and along an interconnect line. The contact hole and trench are filled, for example, as in the previous method, with a titanium adhesion layer, a titanium-tungsten or -nitride barrier layer, and a tungsten blanket layer. In the Damascene process, the tungsten blanket layer in the trench is the interconnect and forms the contact with an overlying conductive material.
Referring back to the titanium, titanium-tungsten or -nitride, tungsten contact/interconnect process described above and illustrated in FIG. 1, a typical device process will overlay the structure shown in FIG. 1 with a second insulating layer. FIG. 2 illustrates the deposition of a second planarized insulating layer 220 and the opening of the insulating layer 220 to form a second contact hole 230 above the interconnect 240. The second contact hole 230 is formed by etching the second insulating layer 220 whereby a second contact hole 230 is exposed above the interconnect 240. To compensate for misalignment and to assure that electrical connection between the interconnect 240 and a subsequent contact in the second contact hole 230, the over etch of the exposed interconnect 240 region must be large to account for the uniformity of the equipment.
The result of this large, thorough over etch to assure the exposure of the interconnect is that the underlying first insulating layer is gouged in the area not covered by the interconnect. The gouge or trench 250 occurs because the selectivity of the second insulating layer 220 etch cannot limit the etch to the removal of only second insulating layer material (typically an oxide material), but inevitably involves the etching of the first insulating layer 210 (typically, also an oxide material) that is unprotected by interconnect. In other words, the second insulating layer 220 is selective in that it will etch insulating material and not interconnect material, but will also continue beyond the second insulating layer 220 and etch the first insulating material in the contact area where there is an absence of interconnect material. The gouge or trench 250 created is undesirable because the gouge 250 can fill with contaminants that will shorten the life of the integrated circuit.
To avoid the resultant gouge or trench and possible contamination, the prior art creates "enlarged landing pads" of the interconnect material. An enlarged landing pad is an enlarged portion of the interconnect material that is designed to assure contact with the contact material and protect against gouging. To compensate for misalignment and to avoid the creation of a gouge or trench, an enlarged landing pad is usually created by patterning with a mask and etching the interconnect material. The connection point (or landing pad) between the contact and the interconnect is made to extend to the furthest point of potential misalignment of the contact hole given the process margin, i.e., the enlarged landing pad occupies the largest possible surface area that a subsequent contact may contact plus an additional area to serve as an etch-stop layer to prevent gouging. FIG. 3 presents a top plan view of a device with two interconnects 310, 315 with enlarged landing pads 320, 325 overlying a first insulating layer. FIG. 3 is not drawn to the same scale as FIG. 2 so that the enlarged landing pads of the prior art may be clearly illustrated. The enlarged landing pads 320, 325 occupy considerably more surface area than the interconnect lines 310, 315. For clarity purposes a second insulating layer is not shown over the interconnects 310, 315. In FIG. 3, interconnect 310 is electrically linked to the first contact opening 330. A second contact opening 340 (shown in ghost lines) for an upper layer interconnect is made to the landing pad 320 of interconnect 310.
The size of prior art enlarged landing pads is proportional to the device technology utilized. For example, with 0.5 .mu.m technology, the contact opening is approximately 0.5 .mu.m which means that the interconnect material need be only 0.5 .mu.m wide to be in complete contact with conductive material in the contact opening. However, because of alignment tolerances and to avoid the creation of the gouge or trench, prior art processes typically add at least an additional 0.25 .mu.m to each side of the contact point of the interconnect to create an enlarged landing pad of interconnect material.
The eventual size of the landing pad of the interconnect is directly related to the spacing of active structures on an integrated circuit. In other words, the spacing requirement mandated by the need for a significant landing pad limits the density of the device being fabricated as the contact openings must be safely constructed so as not to allow the introduction of contaminants into the structure by an unwanted gouge or trench. Enlarged landing pads with enlarged surface areas reduce the number of interconnects that may be placed in a given location on a device.
There is a need for a process to create and electrically link interconnects of reduced geometry with overlying contact structures. The reduced geometry interconnects must be part of a process whereby the insulating layer over which the interconnects lie is not gouged. Finally, there is a need for simpler interconnect-contact formation process that maximizes device space.